A 128-channel time-to-digital converter based on the shifted clock sampling method has successfully been implemented in a single Virtex-5 FPGA on the GANDALF module. The TDC base clock has a frequency of 388.8 MHz. The 128-channel TDC design is segmented into 16 identical blocks of 8 channels each, the F1-block. This is done to ease the data collection process by using a two-step procedure. The timestamps of the detected hits are stored in a 1k deep hit buffer per channel. The timestamps of incoming triggers are buffered in a trigger FIFO, until they are processed by the trigger matching unit. This algorithm combines 8 channels at a time by selecting the hits from the respective hit buffers that fall into the trigger window and writing them to the output FIFO of the F1-block. In a last step the data from all 16 F1-blocks are collected and sent to the DAQ using the S-Link interface.